International Workshop on

Metal Gate/Workfunction Science and Engineering

Braun Auditorium, Stanford University

Thursday, August 28

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Overview (Session Chair: Luigi Colombo)

8:15 Introduction

Yoshio Nishi, Stanford University

8:35 Metal gate work function needs from device perspective

Y. Taur, UC-San Diego

9:10 CMOS scaling limits with high K/metal gate

H. Iwai, Tokyo Institute of Technology

9:45 Planar CMOS and alternative structures

D. Antoniadis, MIT

10:20 – 10:50 Break

Physics of Workfunctions (Session Chair: Luigi Colombo)

10:50 Understanding Workfunctions

W. Harrison, Stanford University

11:25 Spectroscopic determination of workfunctions

P. Pianetta, Stanford University

12:00-1:35 Lunch Break/Posters

Metal Gate Approaches for CMOS (Session Chair: Yoshio Nishi)

1:35 Variation of effective work function of TaNx gates by high temperature annealing

T. Nabatame, AIST

2:10 Multilayer Metallic Gate Electrode for Depletion Suppression and Tunable Workfunction

S. Hung, Applied Materials

2:45 – 3:15 Break

3:15 Tunable-work-function gate technology

T. J. King, UC-Berkeley

3:50 Metal gate CMOS integration challenges

M. Rodder, Texas Instruments

4:25 Work function Tuning, Thermal Stability and Process Compatibility of Dual Metal Gate Electrodes

V. Misra, North Carolina State University

5:30-9:30 Stanford Faculty Club Reception, Dinner & Panel Discussion

Moderator: Paul McIntyre

Panel: Bin Yu, R. Wallace, K. Goto, D. Antoniadis, S. Guha, V. Misra

 

Friday, August 29

 

Metal Dielectric Interface Structure and Physics (Session Chair: Chris Chidsey)

8:30 Ab initio Study of Metal Electrode Work function

K. J. Cho, Stanford University

9:05 Band offsets and work functions in high K gate oxide stacks

J. Robertson, Engineering Dept, Cambridge University

9:40 Gate/dielectric interface reactions

R. Wallace, UT-Dallas

10:15 – 10:45 Break

Mobility, High-k, SiON, Metal Gates and Strained Si (Theory and Experiment)

(Session Chair: Paul McIntyre)

10:45 Integration issues: metal gates on high mobility substrates

S. Biesemans, IMEC

11:20 Material aspects of high K gate integration

S. Guha, IBM T. J. Watson Research Center

11:55 Metal gate high-k Ge channel MOSFETs

C.-O. Chui, Stanford University

12:30 – 1:30 Lunch Break

Electrodes and Contacts (Session Chair: Luigi Colombo)

1:30 Low Resistance Metal S/D MOSFET Engineering

D. Connelly, Acorn Technology

2:05 Channel and Source/Drain Engineering in Ultrathin body MOSFETs

K. Uchida, Toshiba

2:40 Application and issues of silicides and stress controlled CMOS

K. Goto, Fujitsu